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Programare microcontroller (PIC16F15376)

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#1
T1000Android

T1000Android

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Salut.

Incerc sa invat programarea si structura microcontroller-ului PIC16F15376 jucandu-ma cu cate un bloc o data si am dat de o problema. Pentru Timer1 nu reusesc sa obtin o frecventa mare (cativa MHz) la iesirea blocului CCP1 (pagina 357 in datasheet); in schimb obtin 245Hz (pe osciloscop) pe pinul RC3 la fiecare al 3-lea upload al codului (trebuie sa incarc codul de 3 ori pentru a obtine 245Hz; in rest obtin logic high sau low). Mai jos atasez codul si datasheet-ul, pentru cine este interesat sa ma ajute.

Ma intereseaza ce anume nu setez bine in bitii de control al blocurilor.

Merci mult.

/*
* File:   main.c
* Author: X
*
* Created on May 11, 2020, 6:03 PM
*/
// PIC16F15376 Configuration Bit Settings
// 'C' source line config statements
// CONFIG1
#pragma config FEXTOSC = OFF	// External Oscillator mode selection bits (Oscillator not enabled)
#pragma config RSTOSC = HFINT32 // Power-up default value for COSC bits (HFINTOSC with OSCFRQ= 32 MHz and CDIV = 1:1)
#pragma config CLKOUTEN = ON	// Clock Out Enable bit (CLKOUT function is enabled; FOSC/4 clock appears at OSC2 (RA6))
#pragma config CSWEN = ON	   // Clock Switch Enable bit (Writing to NOSC and NDIV is allowed)
#pragma config FCMEN = OFF	  // Fail-Safe Clock Monitor Enable bit (FSCM timer disabled)
// CONFIG2
#pragma config MCLRE = OFF	  // Master Clear Enable bit (MCLR pin function is port defined function)
#pragma config PWRTE = OFF	  // Power-up Timer Enable bit (PWRT disabled)
#pragma config LPBOREN = OFF	// Low-Power BOR enable bit (ULPBOR disabled)
#pragma config BOREN = OFF	  // Brown-out reset enable bits (Brown-out reset disabled)
#pragma config BORV = LO		// Brown-out Reset Voltage Selection (Brown-out Reset Voltage (VBOR) set to 1.9V on LF, and 2.45V on F Devices)
#pragma config ZCD = OFF		// Zero-cross detect disable (Zero-cross detect circuit is disabled at POR.)
#pragma config PPS1WAY = OFF	// Peripheral Pin Select one-way control (The PPSLOCK bit can be set and cleared repeatedly by software)
#pragma config STVREN = OFF	 // Stack Overflow/Underflow Reset Enable bit (Stack Overflow or Underflow will not cause a reset)
// CONFIG3
#pragma config WDTCPS = WDTCPS_31// WDT Period Select bits (Divider ratio 1:65536; software control of WDTPS)
#pragma config WDTE = OFF	   // WDT operating mode (WDT Disabled, SWDTEN is ignored)
#pragma config WDTCWS = WDTCWS_7// WDT Window Select bits (window always open (100%); software control; keyed access not required)
#pragma config WDTCCS = SC	  // WDT input clock selector (Software Control)
// CONFIG4
#pragma config BBSIZE = BB512   // Boot Block Size Selection bits (512 words boot block size)
#pragma config BBEN = OFF	   // Boot Block Enable bit (Boot Block disabled)
#pragma config SAFEN = OFF	  // SAF Enable bit (SAF disabled)
#pragma config WRTAPP = OFF	 // Application Block Write Protection bit (Application Block not write protected)
#pragma config WRTB = OFF	   // Boot Block Write Protection bit (Boot Block not write protected)
#pragma config WRTC = OFF	   // Configuration Register Write Protection bit (Configuration Register not write protected)
#pragma config WRTSAF = OFF	 // Storage Area Flash Write Protection bit (SAF not write protected)
#pragma config LVP = OFF		// Low Voltage Programming Enable bit (High Voltage on MCLR/Vpp must be used for programming)
// CONFIG5
#pragma config CP = OFF		 // UserNVM Program memory code protection bit (UserNVM code protection disabled)
// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.
#include <xc.h>
#define _XTAL_FREQ 32000000
const int delayTime = 100;
void main(void) {
   
	//setup output
	TRISC3 = 0;
	RC3PPS = 0x09; // output remapping options on page 240 (capture/ compare module out is on RC3)
	__delay_us(delayTime);
   
	//setup timer1 module
	T1CON = 0b00000111; // reg on page 331
	T1GCON = 0b00000000; // timer1 gate control (reg on page 332) - gate is disabled
	T1GATE = 0b00000000; // for timer1 controlled by gate
	T1CLK = 0b00000011; // timer1 input clock selection (HFINTOSC) (reg on page 333)
	__delay_us(delayTime);
   
	//setup CCP1 module in compare mode (for output) with timer1 as input
	CCP1CON = 0b10000001; // set output to toggle on TMR1(H/L) = CCPR1(H/L)(reg at page 364)
	CCPR1L = 0b00000111; // set lower bits of compare reg
	CCPR1H = 0b00000000; // set higher bits of compare reg
	__delay_us(delayTime);
   
   
	//test/debug
	//TMR1L = 0b00000011; // manually set TMR1(H/L) to see if the selected output toggles (for test-debug purposes)
	//TMR1H = 0b00000000;
   
	while(1){}
   
}



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