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Chirurgia spinală minim invazivă
Chirurgia spinală minim invazivă oferă pacienților oportunitatea unui tratament eficient, permițându-le o recuperare ultra rapidă și nu în ultimul rând minimizând leziunile induse chirurgical. Echipa noastră utilizează un spectru larg de tehnici minim invazive, din care enumerăm câteva: endoscopia cu variantele ei (transnazală, transtoracică, transmusculară, etc), microscopul operator, abordurile trans tubulare și nu în ultimul rând infiltrațiile la toate nivelurile coloanei vertebrale. www.neurohope.ro |
Intel CPU - Design flaw in fiecare procesor din ultimii 10 ani
7 votes
Last Updated: Mar 12 2021 19:26, Started by
ct03nut
, Jan 03 2018 09:08
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#1406
Posted 10 May 2018 - 13:20
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Mai cateva patchuri : https://cve.mitre.or...e=CVE-2018-8897 si ajungi din urma r3 1200 ;>
P.S.Parca urla o clona pe aici acum cateva luni ca AMD trimise documentatie gresita la Microsoft de lasa Athloanele nebootabile ;] Iote ca Intel trimise la toata lumea documentatie "gresita" ;> Edited by Arthos, 10 May 2018 - 13:26. |
#1407
Posted 20 May 2018 - 13:45
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Un update de la un fost inginer Intel : https://www.linkedin.com/in/bulygin
https://blog.eclypsi...cution-attacks/ |
#1408
Posted 22 May 2018 - 05:03
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Primele informatii despre variantele 3a si 4 cu impact mediu pentru ca necesita utilizator local.
Intel : Addressing New Research for Side-Channel Analysis Details and Mitigation Information for Variant 4 Quote We’ve already delivered the microcode update for Variant 4 in beta form to OEM system manufacturers and system software vendors, and we expect it will be released into production BIOS and software updates over the coming weeks. This mitigation will be set to off-by-default, providing customers the choice of whether to enable it. We expect most industry software partners will likewise use the default-off option. In this configuration, we have observed no performance impact. If enabled, we’ve observed a performance impact of approximately 2 to 8 percent based on overall scores for benchmarks like SYSmark® 2014 SE and SPEC integer rate on client and server test systems. This same update also includes microcode that addresses Variant 3a (Rogue System Register Read), which was previously documented publicly by Arm* in January. We have not observed any meaningful performance impact on client or server benchmarks with the Variant 3a mitigation.3 We’ve bundled these two microcode updates together to streamline the process for our industry partners and customers. This is something you will see us continue, as we recognize that a more predictable and consolidated update process will be helpful to the entire ecosystem. Intel : Q2 2018 Speculative Execution Side Channel Update ARM : Vulnerability of Speculative Processors to Cache Timing Side-Channel Mechanism AMD: Speculative Store Bypass Vulnerability Mitigations for AMD Platforms Quote AMD recommended mitigations for SSB are being provided by operating system updates back to the Family 15 processors (“Bulldozer” products). For technical details, please see the AMD whitepaper. Microsoft is completing final testing and validation of AMD-specific updates for Windows client and server operating systems, which are expected to be released through their standard update process. Similarly, Linux distributors are developing operating system updates for SSB. AMD recommends checking with your OS provider for specific guidance on schedules. Based on the difficulty to exploit the vulnerability, AMD and our ecosystem partners currently recommend using the default setting that maintains support for memory disambiguation. We have not identified any AMD x86 products susceptible to the Variant 3a vulnerability in our analysis to-date AMD si ARM nu par afectate de varianta 3a. Pentru varianta 4 AMD propune patch software fara microcode. |
#1409
Posted 22 May 2018 - 07:29
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Pentru ca fix-ul e off by default nici un impact asupra performantei ;> Deci, dacă e activată mitigația asta, impactul e între 2 și 8%, pe lângă celelalte impacturi. Edited by Mr_nobody_, 22 May 2018 - 07:31. |
#1410
Posted 09 June 2018 - 04:00
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Cum fac update la BIOS? E periculos? Are rost sa il fac?
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#1411
Posted 09 June 2018 - 14:24
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Cum fac update la BIOS?
E periculos?
Are rost sa il fac? |
#1412
Posted 14 June 2018 - 05:26
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CVE-2018-3665: Lazy State Save/Restore As The Latest CPU Speculative Execution Issue
Intel LazyFP vulnerability: Exploiting lazy FPU state switching Intel chip flaw: Math unit may spill crypto secrets to apps – modern Linux, Windows, BSDs immune INTEL-SA-00145 Leak-ul https://twitter.com/...488038657581056 [ https://www.youtube-nocookie.com/embed/UaQpvXSa4X8?feature=oembed - Pentru incarcare in pagina (embed) Click aici ] https://gitweb.drago...d94db6a75af7dbe TD;LR Patch-ul creste performanta si consumul ;> |
#1415
Posted 14 June 2018 - 17:49
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nu cred ca trebuie sa ne ingrijoram prea tare. avem deja sri/nsa inside. se vor impiedica virusii/hackerii de ei.
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#1416
Posted 14 June 2018 - 21:57
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TD;LR Patch-ul creste performanta si consumul ;> |
#1417
Posted 21 June 2018 - 06:09
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Blackhat 2018 4-9 august : TLBleed: When Protecting Your CPU Caches is Not Enough
https://www.blackhat...ot-enough-10149 Quote We present TLBleed, a novel side-channel attack that leaks information out of Translation Lookaside Buffers (TLBs). TLBleed shows a reliable side channel without relying on the CPU data or instruction caches. This therefore bypasses several proposed CPU cache side-channel protections. Our TLBleed exploit successfully leaks a 256-bit EdDSA key from libgcrypt (used in e.g. GPG) with a 98% success rate after just a single observation of signing operation on a co-resident hyperthread and just 17 seconds of analysis time. Further, we show how another exploit based on TLBleed can leak bits from the side-channel resistant RSA implementation in libgcrypt. We use novel machine learning techniques to acheive this level of performance. These techniques will likely improve the quality of future side-channel attacks. This talk contains details about the architecture and complex behavior of modern, multilevel TLB's on several modern Intel microarchitectures that is undocumented, and will be publically presented for the first time. OpenBSD Disabling SMT / Hyper Threading Due To Security Concerns https://www.phoronix...D-Disabling-SMT Quote Security oriented BSD operating system OpenBSD is making the move to disable Hyper Threading (HT) on Intel CPUs and more broadly moving to disable SMT (Simultaneous Multi Threading) on other CPUs too. Disabling of Intel HT and to follow with disabling SMT for other architectures is being done in the name of security. "SMT (Simultanious Multi Threading) implementations typically share TLBs and L1 caches between threads. This can make cache timing attacks a lot easier and we strongly suspect that this will make several spectre-class bugs exploitable. Especially on Intel's SMT implementation which is better known as Hypter-threading. We really should not run different security domains on different processor threads of the same core." Intel Hyper Threading Performance With A Core i7 On Ubuntu 18.04 LTS https://www.phoronix...l-ht-2018&num=1 Quote Long story short, Hyper Threading is still very much relevant in 2018 with current-generation Intel CPUs. In the threaded workloads that could scale past a few threads, HT/SMT on this Core i7 8700K processor yielded about a 30% performance improvement in many of these real-world test cases. Inca 30% in minus pentru Intel |
#1418
Posted 21 June 2018 - 10:32
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Bai e nasol.
Am adunat toate procentele alea in minus si am scazut din 100% (performanta pe care aveam inainte de izbucnirea isteriei) si am mai ramas cu 7% performanta pe un I7 6700K. Noroc ca e racit cu apa care mai spala putin rusinea de a avea Intel. |
#1419
Posted 21 June 2018 - 15:32
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aceste fix-uri vor veni automat prin windows update si ne vor paradi procesoarele, dezactiva ht etc?
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#1420
Posted 24 July 2018 - 14:55
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Spectre Returns! Speculation Attacks using the Return Stack Buffer : https://arxiv.org/pdf/1807.07940.pdf
Quote
This attack successfully works on fully patched machines. The attack bypasses all software and microcode patches:it bypasses Retpoline since no indirect jumps are used. It bypasses the microcode patches since they do not appear to limit speculation through the RSB. It bypasses RSB refilling (which is only implemented on Skylake+, but not on the Xeon processors) since no mode switches to the kernel are triggered during the attack. Thus, SGX is vulnerable to SpectreRSB even on fully patched machines. |
#1421
Posted 14 August 2018 - 20:55
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Acum ca o trecut si DEFCON-ul si BlackHat-ul avem
L1 Terminal Fault / CVE-2018-3615 , CVE-2018-3620,CVE-2018-3646 / INTEL-SA-00161 https://software.int...-terminal-fault https://www.intel.co...ology/l1tf.html [ https://www.youtube-nocookie.com/embed/kBOsVt0iXE4?feature=oembed - Pentru incarcare in pagina (embed) Click aici ] https://access.redha...ities/L1TF-perf |
#1422
Posted 14 August 2018 - 21:33
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Ăștia de la Intel deja.s nesimțiți. S.au căcat pe ea de securitate în detrimentul vitezei.
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